The technology provides techniques for optimizing transistor-level placement using a hybrid approach involving reinforcement learning (“RL”) in conjunction with an optimization technique. This can include implementing an iterative RL training process for an integrated circuit to train a RL agent, including the RL agent learning an ordering of transistors for the integrated circuit by placement of one transistor on an encoded grid per iteration. The RL agent iterates until all transistors for the integrated circuit are placed on the encoded grid. Upon placing all the transistors on the encoded grid, one or more processors implement a solver module using the ordering of the transistors as an input. The solver module is configured to perform an optimization to minimize spacing between the transistors. The trained reinforcement learning agent can then be save in memory.