Invention Application
- Patent Title: MULTI-GATE TRANSISTOR STRUCTURE WITH ETCH STOP LAYER
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Application No.: US18791275Application Date: 2024-07-31
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Publication No.: US20240395881A1Publication Date: 2024-11-28
- Inventor: Tze-Liang LEE
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L27/092 ; H01L29/06 ; H01L29/40 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/786

Abstract:
A device includes a gate structure, source/drain regions, a first source/drain contact, an etch stop layer, and a first source/drain via. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The first source/drain contact is over a first one of the source/drain regions. The etch stop layer overlaps the gate structure but does not overlap the first source/drain contact. The first source/drain via is over the first source/drain contact. The first source/drain via has a stepped bottom surface structure comprising a lower step in contact with a top surface of the first source/drain contact, an upper step in contact with a top surface of the etch stop layer, and a step rise connecting the lower step and the upper step. The step rise is in contact with a side surface of the etch stop layer.
Information query
IPC分类: