A pixel circuit layer may include a first power line, a sensing line, a second power line, and a data line disposed spaced apart from each other in a first direction and extending in a second direction crossing the first direction, and a sensing control line disposed on one side of the first power line, the sensing line, the second power line, and the data line and extending in the first direction in a plan view. The sensing control line may include a first protrusion extending between the sensing line and the second power line and a second protrusion spaced apart from the first protrusion and extending between the second power line and the data line. The first protrusion may include gate electrodes of a third transistor of the first and second sub-pixels, and the second protrusion may include a gate electrode of a third transistor of the third sub-pixel.