A semiconductor device includes bitlines on a cell region of a substrate; a contact plug between the bitlines; a landing pad on the contact plug; a peripheral gate on a peripheral circuit region of the substrate; a lower interlayer insulating layer covering a side surface of the peripheral gate; a peripheral contact plug penetrating through the lower interlayer insulating layer; peripheral interconnection layers on the lower interlayer insulating layer and the peripheral contact plug; and peripheral insulating structures passing between the peripheral interconnection layers, wherein the peripheral insulating structures include a first peripheral insulating structure partially penetrating through the lower interlayer insulating layer, and wherein the first peripheral insulating structure includes a first peripheral insulating layer, a second peripheral insulating layer on the first peripheral insulating layer and passing between the peripheral interconnection layers, and a mixture layer between the lower interlayer insulating layer and the first peripheral insulating layer.