发明授权
US3700916A Logical frequency divider 失效
逻辑频率分频器

Logical frequency divider
摘要:
A logical frequency divider comprising at least one stage of division by two consisting of four logical gates A, B, C and D, the gates being connected as follows: the output from the first gate A controls an input to the second gate B; the output from the second gate B controls an input to the first gate A and an input to the third gate C; the output from the third gate C controls a second input to the first gate A, a second input to the second gate B and an input to the fourth gate D; the output from the fourth gate D controls a third input to the second gate B, a second input to the third gate C. The input signal to the stage of division by two controls a third input to the third gate C and a second input to the fourth gate D.
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