发明授权
- 专利标题: Logical frequency divider
- 专利标题(中): 逻辑频率分频器
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申请号: US3700916D申请日: 1971-11-15
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公开(公告)号: US3700916A公开(公告)日: 1972-10-24
- 发明人: VITTOZ ERIC ANDRE
- 申请人: CENTRE ELECTRON HORLOGER
- 专利权人: Centre Electron Horloger
- 当前专利权人: Centre Electron Horloger
- 优先权: CH1713870 1970-11-19
- 主分类号: H03K21/00
- IPC分类号: H03K21/00 ; H03K23/58 ; H03K19/34
摘要:
A logical frequency divider comprising at least one stage of division by two consisting of four logical gates A, B, C and D, the gates being connected as follows: the output from the first gate A controls an input to the second gate B; the output from the second gate B controls an input to the first gate A and an input to the third gate C; the output from the third gate C controls a second input to the first gate A, a second input to the second gate B and an input to the fourth gate D; the output from the fourth gate D controls a third input to the second gate B, a second input to the third gate C. The input signal to the stage of division by two controls a third input to the third gate C and a second input to the fourth gate D.
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