发明授权
US3840864A Multiple memory unit controller 失效
多个存储单元控制器

  • 专利标题: Multiple memory unit controller
  • 专利标题(中): 多个存储单元控制器
  • 申请号: US43322774
    申请日: 1974-01-14
  • 公开(公告)号: US3840864A
    公开(公告)日: 1974-10-08
  • 发明人: CHANG HAGGARWAL S
  • 申请人: BURROUGHS CORP
  • 专利权人: Burroughs Corp
  • 当前专利权人: Burroughs Corp
  • 优先权: US43322774 1974-01-14; US19426971 1971-11-01
  • 主分类号: G06F12/06
  • IPC分类号: G06F12/06 G06F13/00
Multiple memory unit controller
摘要:
A memory control unit for determining the actual physical location of an instruction address in one of a plurality of memory units in a digital computer wherein the instruction address and the memory addresses are both in a block, track and word hierarchy, where the instruction address may not correspond to the memory address due to differences in the number of available blocks for recording program instructions from memory unit to memory unit, utilizing: a block address register for storing the block portion of the instruction address; a shift register associated with each memory unit wherein the number of available blocks for each memory unit is stored; a flip flop for bit by bit comparison of the contents of the block address register with the contents of selected shift registers; a counter for shifting from one to another of the shift registers when the contents of the block register exceeds the contents of the selected shift register, and an adder for decrementing the contents of the block address register by an amount equal to the number contained in the previously selected shift register. The memory control unit also includes another flip flop responding to the bit by bit serial comparison of the block address register and the selected shift register for detecting whether the instruction address starts in the last available block in a memory unit, and a circuit for evaluating the track and word portion of the address of each word of the instruction being executed for determining when the last word of an instruction has been executed by the computer.
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