Invention Grant
- Patent Title: Random error correcting system
- Patent Title (中): 随机纠错系统
-
Application No.: US41155273Application Date: 1973-10-31
-
Publication No.: US3873971APublication Date: 1975-03-25
- Inventor: EN JOHN
- Applicant: MOTOROLA INC
- Assignee: Motorola Inc
- Current Assignee: Motorola Inc
- Priority: US41155273 1973-10-31
- Main IPC: H04L1/00
- IPC: H04L1/00 ; G06F11/12
Abstract:
A rate one half random error correcting convolutional coding system capable of correctng two out of any twelve information and parity bits having an encoder comprising a six stage shift register and a modulo 2 adder connected to the shift register for combining the first, fourth, fifth and sixth information bits present in the register to generate parity bits which are subsequently interleaved with the information bits. A decoder employing another six stage shift register generates syndrom bits by combining parity bits generated from the received information with the received parity bits. The syndrome bits are applied to a six stage syndrome register which is coupled, both directly and via other modulo 2 adder, to a majority logic circuit which provides a correcting signal when the number of ones applied thereto exceeds a predetermined number.
Information query