Correct data stored in an overlay memory register is furnished to a processor, instead of incorrect data stored in a fixed memory register addressed by the processor, by providing a mapping memory that is addressed simultaneously with the addressing of the overlay memory and the fixed memory. The mapping memory is connected with the overlay memory and the fixed memory such that the state of the addressed mapping memory register will enable either the fixed memory or the overlay memory to carry out a data transfer to the processor. The states of the mapping memory registers are preselected in accordance with knowledge of which of the fixed memory registers contains incorrect data. When the processor addresses a fixed memory register containing incorrect data, the state of the addressed mapping memory register will be such as to disable the fixed memory thereby precluding it from transferring incorrect data to the processor, and, simultaneously, to enable the overlay memory thereby allowing the addressed overlay memory register to transfer correct data to the processor.