发明授权
US4276515A Differential amplifier circuit arrangement with stabilized input
impedance
失效
具有稳定输入阻抗的差分放大器电路布置
- 专利标题: Differential amplifier circuit arrangement with stabilized input impedance
- 专利标题(中): 具有稳定输入阻抗的差分放大器电路布置
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申请号: US12701申请日: 1979-02-16
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公开(公告)号: US4276515A公开(公告)日: 1981-06-30
- 发明人: Yutaka Nishimoto
- 申请人: Yutaka Nishimoto
- 申请人地址: JPX Hamamatsu
- 专利权人: Nippon Gakki Seizo Kabushiki Kaisha
- 当前专利权人: Nippon Gakki Seizo Kabushiki Kaisha
- 当前专利权人地址: JPX Hamamatsu
- 优先权: JPX53-25989[U] 19780301
- 主分类号: H03F1/32
- IPC分类号: H03F1/32 ; H03F1/56 ; H03F3/45
摘要:
A differential amplifier circuit arrangement provided with first and second field effect transistors having their sources coupled together in common, the drain of the first field effect transistor being connected to the emitter of a bipolar transistor whose collector is connected via a drain load for this field effect transistor to a power supply line and whose base is held at a constant potential with respect to the commonly coupled sources, the drain of the second field effect transistor being coupled to the power supply line without a voltage stabilizing transistor. The bipolar transistor serves to stabilize the drain-source voltage of the first field effect transistor, thus maintaining constant the input impedance of the amplifier measured at the gate of the first field effect transistor. The differential transistors may be bipolar transistors.
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