发明授权
US4289550A Method of forming closely spaced device regions utilizing selective
etching and diffusion
失效
利用选择性蚀刻和扩散形成紧密间隔的器件区域的方法
- 专利标题: Method of forming closely spaced device regions utilizing selective etching and diffusion
- 专利标题(中): 利用选择性蚀刻和扩散形成紧密间隔的器件区域的方法
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申请号: US42686申请日: 1979-05-25
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公开(公告)号: US4289550A公开(公告)日: 1981-09-15
- 发明人: Wolfgang M. Feist
- 申请人: Wolfgang M. Feist
- 申请人地址: MA Lexington
- 专利权人: Raytheon Company
- 当前专利权人: Raytheon Company
- 当前专利权人地址: MA Lexington
- 主分类号: H01L21/8222
- IPC分类号: H01L21/8222 ; H01L21/306 ; H01L21/331 ; H01L21/76 ; H01L21/762 ; H01L27/06 ; H01L29/10 ; H01L29/73 ; H01L29/737 ; H01L21/20 ; H01L21/302
摘要:
A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.