发明授权
- 专利标题: Memory circuit with increased operating speed
- 专利标题(中): 内存电路具有提高的运行速度
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申请号: US89745申请日: 1979-10-31
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公开(公告)号: US4300213A公开(公告)日: 1981-11-10
- 发明人: Nobuyoshi Tanimura , Hiroshi Fukuta , Kotaro Nishimura , Tokumasa Yasui
- 申请人: Nobuyoshi Tanimura , Hiroshi Fukuta , Kotaro Nishimura , Tokumasa Yasui
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi Ome Electronic Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Ome Electronic Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX53-144133 19781124
- 主分类号: G11C11/412
- IPC分类号: G11C11/412 ; G11C11/417 ; H03K19/0185 ; H03K19/0944 ; G11C7/00
摘要:
Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.
公开/授权文献
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