发明授权
- 专利标题: Circuit for reducing the limit cycle in a digital filter
- 专利标题(中): 降低数字滤波器极限周期的电路
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申请号: US095554申请日: 1979-11-19
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公开(公告)号: US4321685A公开(公告)日: 1982-03-23
- 发明人: Masao Kasuga , Masaki Satoh , Takashi Matsushige
- 申请人: Masao Kasuga , Masaki Satoh , Takashi Matsushige
- 专利权人: Masao Kasuga,Masaki Satoh,Takashi Matsushige
- 当前专利权人: Masao Kasuga,Masaki Satoh,Takashi Matsushige
- 优先权: JPX53-143179 19781120; JPX53-144120 19781124; JPX53-158662 19781225
- 主分类号: H03H17/04
- IPC分类号: H03H17/04 ; G06F15/31
摘要:
A circuit arrangement of a digital filter comprises an A/D converter supplied with an input analog signal and producing as output a pulse-modulated digital signal, a digital filter for subjecting the digital signal from the A/D converter to a digital operation processing of finite word length, a D/A converter supplied with the resulting output digital signal of the digital filter and converting the same into an analog signal thereby to generate an output analog signal, an input detector for detecting the state wherein there is substantially no input analog signal and responsively producing as output a detection signal, an integrator for integrating the output of the D/A converter, a switching circuit for operating in response to the output detection signal of the input detector to pass the resulting output signal of the integrator, a reference voltage source, and an adder for adding the signal thus passed by the switching circuit and a reference voltage from the reference voltage source and feeding back and imparting the sum signal thus obtained to the A/D converter.
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