An addressing system for use with a computer system having a plurality of processing units connected to independent address buses and a plurality of memories connectable to any of the address buses and given a series of addresses. Each processing unit is connected to an address modification register and an adder connected to its address bus. The address content outputted from the processing unit and the content of the address modification register are added together by the adder. The added output is sent on the address bus to address a desired one of the memories. This system permits easy modification of memory allocation and enhances the operation speed of each processing unit.