A transistor circuit (18) is series connected with a solid state switching device (14) and a load (4) controlled by that device (14) to protect that device (14) from overcurrents resulting from short circuits such as across the load (4). The transistor circuit (18) detects the overcurrent and switches to a high impedance state in response to that detection. The circuit (18) is self-resettable to restore to the low impedance state each half-cycle of applied voltage, thereby to automatically restore the switching device (14) to normal operation immediately upon removal of the short, and is set to initially respond to a level of current sufficiently high to preclude switching in response to inrush currents. Initial switching of the circuit (18) to its high impedance state latches a reduced level detection circuit (R1-R2-Q4) in the transistor circuitry (18) whereby the latter switches to its high impedance state upon detecting lower overcurrent values for each successive half-cycle until the short is removed. The predictability of the response range for the circuit, especially in the reduced level voltage detection mode, is improved by placing a resistor (R5) in series with the control switching transistor (Q3) for the circuit.