Invention Grant
- Patent Title: Electronic impedance circuit including a compensation arrangement for d.c. offset
- Patent Title (中): 电子阻抗电路包括直流补偿装置。 抵消
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Application No.: US411997Application Date: 1982-08-27
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Publication No.: US4520282APublication Date: 1985-05-28
- Inventor: Kazuo Watanabe , Yuichi Ohkubo , Akira Haeno , Fumihiko Yokogawa
- Applicant: Kazuo Watanabe , Yuichi Ohkubo , Akira Haeno , Fumihiko Yokogawa
- Applicant Address: JPX Tokyo JPX Tokyo
- Assignee: Hitachi, Ltd.,Pioneer Electronic Corporation
- Current Assignee: Hitachi, Ltd.,Pioneer Electronic Corporation
- Current Assignee Address: JPX Tokyo JPX Tokyo
- Priority: JPX56-134006 19810828
- Main IPC: H03G3/10
- IPC: H03G3/10 ; H03F3/45 ; H03H11/02 ; H03H11/46 ; H03K3/023 ; H03H11/00

Abstract:
An electronic impedance circuit is constructed of a voltage-current converter and a variable gain current amplifier. The voltage-current converter includes first and second transistors of the PNP-type differentially connected. The variable gain current amplifier includes third and fourth transistors of the NPN-type differentially connected, and fifth and sixth transistors of the PNP-type as load means. The bases of the third and fourth transistors are respectively driven by collector signals of the first and second transistors, and a collector signal of the third transistor is fed back to the base of the second transistor. In order to reduce a d.c. offset attributed to a current flowing between the base of the second transistor and the collector of the third transistor, a compensation circuit is connected to the variable gain amplifier. This compensation circuit can provide compensation by producing a compensation current for cancelling the current between the base of the second transistor and the collector of the third transistor.
Public/Granted literature
- US4958540A Impact tool handle Public/Granted day:1990-09-25
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