Invention Grant
US4556952A Refresh circuit for dynamic memory of a data processor employing a
direct memory access controller
失效
采用直接存储器存取控制器的数据处理器的动态存储器刷新电路
- Patent Title: Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
- Patent Title (中): 采用直接存储器存取控制器的数据处理器的动态存储器刷新电路
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Application No.: US292075Application Date: 1981-08-12
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Publication No.: US4556952APublication Date: 1985-12-03
- Inventor: James A. Brewer , Lewis C. Eggebrecht , David A. Kummer , Patricia P. McHugh
- Applicant: James A. Brewer , Lewis C. Eggebrecht , David A. Kummer , Patricia P. McHugh
- Applicant Address: NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: NY Armonk
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G11C11/406 ; G06F13/00
Abstract:
In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.
Public/Granted literature
- US6031751A Small volume heat sink/electronic assembly Public/Granted day:2000-02-29
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