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US4570090A High-speed sense amplifier circuit with inhibit capability 失效
具有抑制能力的高速读出放大器电路

High-speed sense amplifier circuit with inhibit capability
摘要:
A sense amplifier circuit for use with a directory memory chip in which the output of a corresponding memory cell is sensed and output signals representing the sensed bit state are provided to first and second output ports. The signal provided to the first output port can be selectively inhibited, although, when not inhibited, the signals applied to the first and second output ports occur simultaneously. The inhibiting function may be performed by a dual-emitter circuit and switchable current source in one of two sense amplifiers.
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