A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transistor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.