The illustrated receiver 6, in flip-flops 16A-D, stores four sequential samples of a biphase-L signal A1 and shifts the samples into four shift registers 24A-D. The sampled signals are clocked through their respective shift registers 24A-D by selected phases of multiphase clock .phi..sub.1, .phi..sub.2, .phi..sub.3, .phi..sub.4. Thus, each set of four samples is stationary at some location in their respective shift registers for the same clock cycle. A decoder section 10 responds to a transition between adjacent signal levels at the output of the shift registers 24A-D and to a previously sampled signal level A44. The decoder section 10 generates a control signal A32-D32 indicating the detection of a mid-bit biphase-L signal transition. A second storage means responds to the control signal A32-D32 and stores a shift register 24A-D signal level A19, B20-D20 which occurred subsequent to the detected mid-cell transition. The control signal A 32-D32 also synchronizes a recovered clock signal A14 used to clock recovered data A50 to external circuitry.