发明授权
- 专利标题： Process for fabricating semiconductor integrated circuit device
- 专利标题（中）： 制造半导体集成电路器件的工艺
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申请号： US712760申请日： 1985-03-18
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公开(公告)号： US4637124A公开(公告)日： 1987-01-20
- 发明人: Kousuke Okuyama , Norio Suzuki , Satoshi Meguro , Kouichi Nagasawa
- 申请人： Kousuke Okuyama , Norio Suzuki , Satoshi Meguro , Kouichi Nagasawa
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX59-49042 19840316
- 主分类号： H01L27/092
- IPC分类号： H01L27/092 ; H01L21/336 ; H01L21/8234 ; H01L21/8238 ; H01L27/088 ; H01L29/41 ; H01L29/417 ; H01L29/423 ; H01L29/78 ; H01L21/38
摘要：
Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.
公开/授权文献
- US5856684A High power HFET with improved channel interfaces 公开/授权日：1999-01-05
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