发明授权
US4675837A Digital arithmetic unit having shortened processing time and a
simplified structure
失效
具有缩短处理时间和简化结构的数字运算单元
- 专利标题： Digital arithmetic unit having shortened processing time and a simplified structure
- 专利标题（中）： 具有缩短处理时间和简化结构的数字运算单元
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申请号： US619185申请日： 1984-06-11
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公开(公告)号： US4675837A公开(公告)日： 1987-06-23
- 发明人: Walter Ulbrich , Alois Rainer , Tobias Noll
- 申请人： Walter Ulbrich , Alois Rainer , Tobias Noll
- 申请人地址： DEX Berlin and Munich
- 专利权人： Siemens Aktiengesellschaft
- 当前专利权人： Siemens Aktiengesellschaft
- 当前专利权人地址： DEX Berlin and Munich
- 优先权： DEX3323607 19830630
- 主分类号： G06F7/505
- IPC分类号： G06F7/505 ; G06F7/50 ; G06F7/507 ; G06F7/508 ; G06F7/52
摘要：
A digital arithmetic unit useful in data processing digital circuits comprises a plurality of stages each having two half-adders combined into a full adder and a carry logic element. An objective is to shorten the processing time for the addition and subtraction of binary numbers. For this purpose, the stages are divided into at least two groups and two separate carry paths are provided within each group. One of the carry paths is only switched on by means of selection logic elements. The activation occurs sequentially in group-wise fashion after simultaneous carry runs in all carry paths. The advantage particularly consists of the chronological coincidence of the carry runs in all groups.
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