The middle value selection circuit includes three high value selection circuits and one low value selection circuit. Each high value selection circuit consists of a pair of first NPN transistors and a first constant current circuit. The emitter of each first NPN transistor of the high value selection circuit is connected to the first constant current circuit and the base of the second NPN transistor of the low value selection circuit. The base of this second NPN transistor is connected to the second constant current circuit and to an output terminal. The collector of the second NPN transistor is connected to its base. The first constant current circuit produces a current whichis twice the output current of the second constant current circuit. Two analog signals having mutually different combination among three input analog signals are applied to the NPN transistors of one high value selection circuit. The analog signal having a greater value of the two analog signals is generated at the junction of the emitters of these NPN transistors. The analog signals, each representative of the greater value, from the high value selection circuits are applied the emitter of the second NPN transistor. The low value selection circuit produces an analog signal representative of the minimal value among the analog signals applied to the three second NPN transistors.