发明授权
- 专利标题: Self-synchronizing scrambler
- 专利标题(中): 自同步扰频器
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申请号: US739700申请日: 1985-05-31
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公开(公告)号: US4744104A公开(公告)日: 1988-05-10
- 发明人: Reginhard Pospischil
- 申请人: Reginhard Pospischil
- 申请人地址: DEX Berlin and Munich
- 专利权人: Siemens Aktiengesellschaft
- 当前专利权人: Siemens Aktiengesellschaft
- 当前专利权人地址: DEX Berlin and Munich
- 优先权: DEX3420801 19840604
- 主分类号: H03M5/00
- IPC分类号: H03M5/00 ; H04L7/00 ; H04L9/06 ; H04L9/12 ; H04L9/14 ; H04L9/22 ; H04L25/03 ; H04L25/48 ; H04L25/49 ; H04L9/00
摘要:
A self-synchronizing scrambler for high bit rates has a number of scrambler stages supplied in parallel with bits of a signal to be scrambled, each scrambler stage having a series-connected pair of modulo-2 adders, and at least one shift register. A selected number of scrambler stages in the scrambler may include an additional shift register depending upon the number p of parallel bits in the signal to be scrambled, and the total number n of shift registers in the scrambler. The number of scrambler stages having two shift registers is n-p and the number of following scrambler stages having one shift register is 2 p-n. For suppressing short periods, a further modulo-2 adder can be connected between the original two modulo-2 adders, the additional modulo-2 adder inverting at least one bit of the signal for the short periods.
公开/授权文献
- US5930006A Image editing apparatus 公开/授权日:1999-07-27
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