发明授权
US4757467A Apparatus for estimating the square root of digital samples 失效
用于估计数字样本平方根的装置

Apparatus for estimating the square root of digital samples
摘要:
Circuitry for calculating the square root of a binary number iterates the equation E(K+1)=E(K)+(S-E(K).sup.2) where E(K+1) is the current estimate of the square root of the sample S and E(K) is the previous estimate. The value E(K).sup.2 is estimated in order to reduce the complexity of the hardware. An application is described for real time processing of digital audio signals in serial-bit format.
公开/授权文献
信息查询
0/0