A video game home computer is implemented in NMOS (n type metal oxide semiconductor) technology with plural microprocessors. Centralized bus architecture and direct memory access (DMA) techniques are employed. A video display generator provides color signal outputs to drive a commercial television receiver display. This display generator receives inputs from both microprocessors and obtains data directly from memory. A bit map of display information is kept in memory, wherein bits of information in memory image the precise screen display for each instance in time. A bit map manipulator circuit performs, under microprocessor direction, logic function manipulation of the bit map data. Access between system components is accomplished via the bus architecture on a priority queue basis. Chip count and chip area is minimized.