发明授权
- 专利标题: Noise pulse suppressing circuit in digital system
- 专利标题(中): 数字系统中的噪声脉冲抑制电路
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申请号: US39337申请日: 1987-04-17
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公开(公告)号: US4786823A公开(公告)日: 1988-11-22
- 发明人: Masato Abe , Fumitaka Asami
- 申请人: Masato Abe , Fumitaka Asami
- 申请人地址: JPX Kanagawa
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kanagawa
- 优先权: JPX61-89599 19860418
- 主分类号: H03H17/00
- IPC分类号: H03H17/00 ; H03K3/13 ; H03K5/1252 ; H03K5/22
摘要:
Noise pulses having both polarities which are superposed on an input signal having a binary state of H/L levels forming a rectangular waveform, are suppressed or eliminated before transferring the input signal to an output stage. A noise pulse suppressing circuit is provided which comprises a latch circuit, a counter circuit, and a logic circuit including NAND gates and INVERTERs. For the latch circuit and the counter circuit, D-type flip-flops are also utilized. The input signal is inputted to a data input terminal of a flip-flop of the latch circuit and outputted from the data output terminal thereof. The latch circuits are triggered by a pulse signal applied to a clock terminal thereof. The above triggering pulse signal is generated by the counter circuit and the logic circuit, and it has a short pulse waveform responding to the input signal but delayed. No pulse in the output is produced which corresponds to the noise pulses in the input signal.
公开/授权文献
- US6043697A Clock signal control apparatus for data output buffer 公开/授权日:2000-03-28