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US4787047A Electrically erasable fused programmable logic array 失效
电可擦除可编程逻辑阵列

  • Patent Title: Electrically erasable fused programmable logic array
  • Patent Title (中): 电可擦除可编程逻辑阵列
  • Application No.: US714866
    Application Date: 1985-03-22
  • Publication No.: US4787047A
    Publication Date: 1988-11-22
  • Inventor: James Y. Wei
  • Applicant: James Y. Wei
  • Applicant Address: CA Santa Clara
  • Assignee: Intersil
  • Current Assignee: Intersil
  • Current Assignee Address: CA Santa Clara
  • Main IPC: H03K19/177
  • IPC: H03K19/177 ;  G06F7/38
Electrically erasable fused programmable logic array
Abstract:
A programmable logic gate array employing a plurality of reprogrammable fuses having a logical NAND characteristic for logically connecting selected inputs to selected logic gates. The fuses are selectively programmed for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.
Abstract(Chinese):

一种可编程逻辑门阵列，其采用具有逻辑NAND特性的多个可重新编程保险丝，用于将所选择的输入逻辑连接到选定的逻辑门。 保险丝被选择性地编程以提供适当的信号以允许逻辑门阵列的三种操作模式; 编程，擦除和正常逻辑运算。

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