发明授权
US4794569A Semiconductor memory having a barrier transistor between a bit line and
a sensing amplifier
失效
具有在位线和感测放大器之间的势垒晶体管的半导体存储器
- 专利标题: Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier
- 专利标题(中): 具有在位线和感测放大器之间的势垒晶体管的半导体存储器
-
申请号: US863190申请日: 1986-05-14
-
公开(公告)号: US4794569A公开(公告)日: 1988-12-27
- 发明人: Hiroshi Sahara , Haruki Toda , Shigeo Ohshima
- 申请人: Hiroshi Sahara , Haruki Toda , Shigeo Ohshima
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX60-114807 19850528
- 主分类号: G11C11/409
- IPC分类号: G11C11/409 ; G11C11/4094 ; G11C11/4096 ; G11C7/00
摘要:
In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.
公开/授权文献
- US5822191A Integrated circuit mounting tape 公开/授权日:1998-10-13
信息查询
IPC分类: