An interface circuit controls the unloading of a host computer system onto a peripheral processor unit. The interface circuit has a normal mode of operation which is independent of the host computer. During the normal mode, the peripheral unit processes data previously supplied by the host computer. The interface device has a trap I/O mode of operation in which information flows between the host computer and the peripheral unit. The trap I/O mode is initiated by a range of instruction addresses from the peripheral unit. In one embodiment, any instruction address less than a predetermined critical value initiates the trap I/O mode. The host computer acknowledges the trap I/O mode, and executes the instruction at the host level to advance the peripheral process. In the trap I/O mode, the peripheral processor operates simultaneous with and independently of the peripheral unit to permit unloading of the host computer. In addition, the peripheral unit has a faster clock and more operating bits than the host system; and can accelerate the processing of the host data.