发明授权
US4857770A Output buffer arrangement for reducing chip noise without speed penalty
失效
输出缓冲器布置，可减少芯片噪声，而不会造成速度损失
- 专利标题： Output buffer arrangement for reducing chip noise without speed penalty
- 专利标题（中）： 输出缓冲器布置，可减少芯片噪声，而不会造成速度损失
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申请号： US161810申请日： 1988-02-29
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公开(公告)号： US4857770A公开(公告)日： 1989-08-15
- 发明人: Hamid Partovi , Michael A. Van Buskirk
- 申请人： Hamid Partovi , Michael A. Van Buskirk
- 申请人地址： CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： CA Sunnyvale
- 主分类号： H03K17/04
- IPC分类号： H03K17/04 ; G11C7/10 ; G11C11/409 ; H03K17/16 ; H03K19/003 ; H03K19/0175 ; H03K19/0185
摘要：
An output buffer arrangement includes a first stable, controlled current source (MO1), a first bidirectional-switching device (24) including a CMOS transmission gate and being responsive to the first current source (MO1) for charging the gate of a pull-up transistor (MO5), a second stable, controlled current source (MO6), and a second bidirectional-switching device (27) including a second CMOS transmission gate and being responsive to the second current source (MO6) for charging the gate of a pull-down transistor (MO10). The output buffer arrangement reduces induced chip noise at low temperature, high power supply voltage without degrading substantially its high operational speed.
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