A pixel processor includes a plurality of pixel slice processors and the architecture is arranged so that the pixel length is extendible by merely increasing the number of pixel slice processors. Each of the pixel slice processors is firstly interconected with other pixel slice processors, and includes a plurality of registers, gates and multiplexers for selectively presenting to a processing means data derived from a variety of sources, including a frame buffer. The output of the processing means can be stored back in the frame buffer or directed to one or more registers in the associated pixel slice processor or/and to registers in other pixel slice processors. SIMD operation is accomplished for pixel lengths which are equal to or larger than the bit capacity of the pixel slice processors. In a particular embodiment of the invention, SIMD operation is effected on pixel lengths larger than the bit capacity of the pixel slice processors. For operating on k pixels simultaneously, the pixel slice processors are grouped into n/i groups of k processors each, where i indicates the bit handling capacity for each pixel slice processor and n is the pixel length.