A synchronizer (100, 102, 104, 106) is disclosed operable in a variety of modes. In a Master/Slave mode the synchronizer receives synchronizing clock signals from a device to which it is a "slave" and generates therefrom synchronizing clock signals to a device to which it is a "master". In a Slave/Slave mode the synchronizer receives synchronizing clock signals from two devices to which it is a slave. In this mode the synchronizer can buffer misalignment between the clocks and report their phase difference for corrective action. In a Slave mode, the synchronizer only receives a synchronizing clock signal. A data-routing multiplexer (50, 108, 110) is employed in conjunction with the synchronizer which allows five devices to be connected to the synchronizer. Signals may be routed between any of the devices. Buffers (112, 120, 122) internal to the data-routing multiplexer perform the frame alignment function.