A data processor which specifies either of a predetermined maximum length of an adddress (a bits) and a length of an address less than the former length and at plural registers having a number of length of bits (r bits) of the maximum address length or greater. The data processor reads out lower-order d bits for data or r bits for an address of the one of the plural registers (7) specified by a first instruction to perform an arithmetic or logic operation, and writes the result into one of the plural registers. Moreover, the processor reads out bits having specified length of an address from the one of the plural registers specified in a second instruction to generate an a-bit address, and reads out d for data or r bits for an address from a main storage device (5) in response to the thus-generated address to write the d or r bits into one of the plural registers. Since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address thereby facilitating extension of the length of a storage address and assuring compatibility with conventional data processors.