发明授权
- 专利标题: Dynamic random access memory device with internal refresh
- 专利标题(中): 具有内部刷新功能的动态随机存取存储器
-
申请号: US141076申请日: 1988-01-05
-
公开(公告)号: US4870620A公开(公告)日: 1989-09-26
- 发明人: Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada , Shigeru Mori , Tetsuya Aono
- 申请人: Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada , Shigeru Mori , Tetsuya Aono
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX62-842 19870106; JPX62-179361 19870717
- 主分类号: G11C8/06
- IPC分类号: G11C8/06 ; G11C11/406
摘要:
The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1. Therefore, malfunctions of the address buffer 1 can be prevented.
公开/授权文献
- US6104988A Electronic control assembly testing system 公开/授权日:2000-08-15