A priority processor (1) and a non-priority processor (20) cooperatively access a common memory (30) by means of an address multiplexer (40) which memory and multiplexer are controlled by a control unit (60). The priority processor issues data strobe (DSSN), clock (CLK) and write control (WSN) signals to the control unit to which the non-polarity processor also issues various memory access request signals. By forming a preparation signal (DSSN=0), the priority processor, through the control unit, claims the memory for a memory access cycle if a prior memory access request by the non-priority processor occurred less than about a clock cycle earlier.