发明授权
- 专利标题: Bit line sense amplifier for programmable logic devices
- 专利标题(中): 用于可编程逻辑器件的位线读出放大器
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申请号: US218556申请日: 1988-07-13
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公开(公告)号: US4899070A公开(公告)日: 1990-02-06
- 发明人: Jung-Hsing Ou , Sau-Ching Wong
- 申请人: Jung-Hsing Ou , Sau-Ching Wong
- 申请人地址: CA Santa Clara
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G11C16/26
- IPC分类号: G11C16/26
摘要:
In a programmable logic device, switching speed is improved by preventing the bit line potential from going excessively close to ground even when large numbers of word line connections to the ground conductor are made. In addition, bit line pull up to logic 1 is effected more rapidly (without retarding bit line pull down to logic 0) by having two transistors connected in parallel with one another between the reference potential source and the bit line. One of these transistors is on all the time providing a relatively small leakage current. The other transistor is on only while the bit line is at logic 0, thereby speeding pull up to logic 1 and then shutting off so as not to impede subsequent return to logic 0.
公开/授权文献
- US4348329A Biocompatible surfaces 公开/授权日:1982-09-07
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