In accordance with the invention, as shown, for example, in FIG. 1, when a second counter 14 attains a number of pulses n needed for period measurement, the time required for n pulses to enter is obtained from a second memory 16, which stores the time that prevailed n pulses ago, and a first memory 15, which stores the time prevailing when the present velocity signal enters. Vehicle velocity is calculated from the time obtained. A second timer 11 is reset whenever the velocity signal enters in order to check the pulse input time interval. When the value in the second timer 11 exceeds a predetermined value t, the second counter 14 is reset in order to remeasure the time required for the n pulses to enter. Thereafter, the contents of the first memory 15 are stored in the second memory 16 and the second timer 11 is also reset. Accordingly, when the value in the second timer 11 exceeds the predetermined value t, namely when the vehicle is traveling at a very low velocity, the system forgoes the calculation of vehicle velocity. As a result, shift signals are not outputted to the shift solenoids on the basis of a vehicle velocity different from the present vehicle velocity and, hence, an erroneous shift does not take place. The arrangement of the system is a simple one since only the clock signal of the microcomputer is utilized.