发明授权
US4907062A Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon 失效
半导体晶片级集成器件由互连的多个芯片组成,每个芯片上形成有集成电路芯片

  • 专利标题: Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon
  • 专利标题(中): 半导体晶片级集成器件由互连的多个芯片组成,每个芯片上形成有集成电路芯片
  • 申请号: US258112
    申请日: 1988-10-14
  • 公开(公告)号: US4907062A
    公开(公告)日: 1990-03-06
  • 发明人: Toshitaka Fukushima
  • 申请人: Toshitaka Fukushima
  • 申请人地址: JPX Kawasaki
  • 专利权人: Fujitsu Limited
  • 当前专利权人: Fujitsu Limited
  • 当前专利权人地址: JPX Kawasaki
  • 优先权: JPX60-222593 19851005
  • 主分类号: H01L23/52
  • IPC分类号: H01L23/52 H01L21/58 H01L23/538 H01L25/065 H01L27/00
Semiconductor wafer-scale integrated device composed of interconnected
multiple chips each having an integration circuit chip formed thereon
摘要:
A device equivalent to a wafer-scale integrated device is achieved by employing multiple IC chips installed on a silicon wafer. For fabricating the device, conventional IC chips of necessary different types are prepared, having their aluminum-wired surfaces coated with a silicon nitride film. These IC chips are placed on a substrate made of silicon keeping the wired faces face up. The wafer may be provided with depressions in which the chips are placed for precise positioning. Upon these chips and the wafer, a silicon layer is grown by a PVD method. The grown silicon layer fills gaps between the IC chips and binds the chips to each other and to the wafer, forming a single piece of wafer. Excessively grown silicon which is taller than the chips is removed by mechano-chemical polishing until the silicon nitride surfaces are exposed. During this polishing process, the silicon nitride film protects the wired surfaces from mechanical and chemical damage. The silicon nitride film is chemically removed until the aluminum wirings are exposed. An insulating layer and aluminum patterning are formed upon the exposed IC chips and filled gaps to form multi-layer wirings for interconnecting the chips and forming input/output connections. This method allows low cost wafer-scale integration higher density wirings and good heat-removal.
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