发明授权
- 专利标题： Pull up circuit for sense lines in a semiconductor memory
- 专利标题（中）： 上拉电路用于半导体存储器中的感测线
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申请号： US252585申请日： 1988-09-30
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公开(公告)号： US4914631A公开(公告)日： 1990-04-03
- 发明人: Gary M. Johnson , Zhitong Chen , Wen-Foo Chern , Ward D. Parkinson , Tyler A. Lowrey , Thomas M. Trent
- 申请人： Gary M. Johnson , Zhitong Chen , Wen-Foo Chern , Ward D. Parkinson , Tyler A. Lowrey , Thomas M. Trent
- 申请人地址： ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： ID Boise
- 主分类号： G11C11/4094
- IPC分类号： G11C11/4094
摘要：
A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).
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