发明授权
- 专利标题： Logic path length reduction using boolean minimization
- 专利标题（中）： 使用布尔最小化的逻辑路径长度缩减
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申请号： US127323申请日： 1987-12-02
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公开(公告)号： US4916627A公开(公告)日： 1990-04-10
- 发明人: David J. Hathaway
- 申请人： David J. Hathaway
- 申请人地址： NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.
公开/授权文献
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