发明授权
US4947319A Arbitral dynamic cache using processor storage 失效
使用处理器存储的仲裁动态缓存

Arbitral dynamic cache using processor storage
摘要:
A data cache in a computer operating system that dynamically adapts its size in response to competing demands for processor storage, and exploits the storage cooperatively with other operating system components. An arbiter is used to determine the appropriate size of the cache based upon competing demands for memory. The arbiter is entered cyclically and samples user's wait states. The arbiter then makes a decision to decrease or increase the size of the cache in accordance with predetermined parameters.
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