发明授权
US4954942A Software debugging system for writing a logical address conversion data
into a trace memory of an emulator
失效
用于将逻辑地址转换数据写入仿真器的跟踪存储器的软件调试系统
- 专利标题： Software debugging system for writing a logical address conversion data into a trace memory of an emulator
- 专利标题（中）： 用于将逻辑地址转换数据写入仿真器的跟踪存储器的软件调试系统
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申请号： US272757申请日： 1988-11-17
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公开(公告)号： US4954942A公开(公告)日： 1990-09-04
- 发明人: Satoshi Masuda , Ikuya Kawasaki , Shigezumi Matsui
- 申请人： Satoshi Masuda , Ikuya Kawasaki , Shigezumi Matsui
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi Ltd.
- 当前专利权人： Hitachi Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX62-293809 19871120
- 主分类号： G06F11/28
- IPC分类号： G06F11/28 ; G06F11/26 ; G06F11/34 ; G06F11/36 ; G06F12/08 ; G06F12/10 ; G06F15/78
摘要：
The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit.
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