发明授权
US4970686A Semiconductor memory cells and semiconductor memory device employing the
semiconductor memory cells
失效
采用半导体存储单元的半导体存储单元和半导体存储器件
- 专利标题： Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells
- 专利标题（中）： 采用半导体存储单元的半导体存储单元和半导体存储器件
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申请号： US396246申请日： 1989-08-21
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公开(公告)号： US4970686A公开(公告)日： 1990-11-13
- 发明人: Yasuo Naruke , Thoru Mochizuki , Taira Iwase , Masamichi Asano
- 申请人： Yasuo Naruke , Thoru Mochizuki , Taira Iwase , Masamichi Asano
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX63-204802 19880819
- 主分类号： G11C17/00
- IPC分类号： G11C17/00 ; G11C17/12 ; G11C17/14 ; G11C29/00 ; G11C29/04
摘要：
A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.
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