发明授权
- 专利标题: Multiplexed serial register architecture for VRAM
- 专利标题(中): 用于VRAM的多路复用串行寄存器架构
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申请号: US446032申请日: 1989-12-05
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公开(公告)号: US4984214A公开(公告)日: 1991-01-08
- 发明人: Nathan R. Hiltebeitel , Robert Tamlyn , Steven W. Tomashot
- 申请人: Nathan R. Hiltebeitel , Robert Tamlyn , Steven W. Tomashot
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G11C11/401
- IPC分类号: G11C11/401 ; G11C11/4096
摘要:
A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.