A reproduced video signal of a VTR is applied to a jitter compensation circuit (100). The applied reproduced video signal is A/D converted by a phase modulated clock and after subjected to the adjustment of timing, the signal is written into a memory (4). A burst signal period is specified based on a timing of a horizontal synchronizing signal in the reproduced video signal and a jitter amount is detected based on a sampling phase of the A/D converted burst. Jitter compensation data is calculated based on this jitter amount. On this occasion, latest jitter compensation data is obtained based on the detected jitter amount and the jitter compensation data one horizontal period before. A timing for starting to write the A/D converted video data into the memory is defined based on high-order data of the calculated jitter compensation data, thereby cancelling large jitter components. On the other hand, a phase of a A/D converting clock is controlled based on low-order data of the jitter compensation data, thereby cancelling small jitter components.