发明授权
- 专利标题: Master-slave flip-flop circuit
- 专利标题(中): 主从触发器电路
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申请号: US349251申请日: 1989-05-09
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公开(公告)号: US5001361A公开(公告)日: 1991-03-19
- 发明人: Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
- 申请人: Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
- 申请人地址: JPX Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX63-114854 19880513; JPX63-117626 19880513
- 主分类号: H03K3/289
- IPC分类号: H03K3/289
摘要:
A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals responsive to the clock signal and outputs at least one of the held complementary output signals. The complementary output signals of the master part have a logic amplitude which is smaller than a logic amplitude of the output signal of the slave part to ensure correct operation even when the data signal and the clock signal have high frequencies.
公开/授权文献
- US6141227A Power supply with reduced second harmonic 公开/授权日:2000-10-31
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