发明授权
- 专利标题： High speed inverting hysteresis TTL buffer circuit
- 专利标题（中）： 高速反相迟滞TTL缓冲电路
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申请号： US473533申请日： 1990-02-01
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公开(公告)号： US5021687A公开(公告)日： 1991-06-04
- 发明人: Roy Yarbrough , Ernest D. Haacke , Lars G. Jansson
- 申请人： Roy Yarbrough , Ernest D. Haacke , Lars G. Jansson
- 申请人地址： CA Santa Clara
- 专利权人： National Semiconductor Corporation
- 当前专利权人： National Semiconductor Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： H03K17/66
- IPC分类号： H03K17/66 ; H03K3/037 ; H03K3/2893 ; H03K19/003 ; H03K19/088
摘要：
A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.