发明授权
US5030852A Quasicomplementary MESFET logic circuit with increased noise imunity
失效
具有增加的噪声影响的基本互补的MESFET逻辑电路
- 专利标题: Quasicomplementary MESFET logic circuit with increased noise imunity
- 专利标题(中): 具有增加的噪声影响的基本互补的MESFET逻辑电路
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申请号: US517626申请日: 1990-05-01
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公开(公告)号: US5030852A公开(公告)日: 1991-07-09
- 发明人: Norio Higashisaka
- 申请人: Norio Higashisaka
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-114528 19890508; JPX2-104307 19900418
- 主分类号: H03K19/0952
- IPC分类号: H03K19/0952
摘要:
Disclosed is a logic circuit performing a quasi-complementary operation. This logic circuit includes a load transistor having a drain connected to a first power supply, a drive transistor having a source connected to a second power supply, a level shift diode connected between a source of the load transistor and a drain of the drive transistor, a resistor connected between a gate of the load transistor and the first power supply, an input portion for applying a signal for complementarily turning on the load transistor and drive transistor in response to an input signal, and a resistor connected between a gate of the drive transistor and the second power supply. Therefore, a gate potential of the load transistor is set to a potential which is always higher than a drain voltage, so as to prevent an output high level from being lowered and expand a logic voltage swing. Further, there is disclosed a logic circuit in which a plurality of quasi-complementary logic circuits are coupled by a wired logic. This circuit configuration enables the number of gate stages to be reduced in case where the plurality of logic circuits are coupled.
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