Invention Grant
- Patent Title: Gate array cell having FETs of different and optimized sizes
- Patent Title (中): 门阵列单元具有不同且优化尺寸的FET
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Application No.: US504153Application Date: 1990-04-03
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Publication No.: US5038192APublication Date: 1991-08-06
- Inventor: Martine Bonneau , Eric Gouze , Robert Hornung , Ieng Ong , Jean-Marc Piccino
- Applicant: Martine Bonneau , Eric Gouze , Robert Hornung , Ieng Ong , Jean-Marc Piccino
- Applicant Address: NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: NY Armonk
- Priority: EPX89480071.3 19890428
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L27/118
Abstract:
A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, . . . ) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g., CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one larger PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, . . . ) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.
Public/Granted literature
- US4518949A Method of A/D conversion by successive approximations Public/Granted day:1985-05-21
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