A cell for use in a packet switching network. The cell comprises an input for receiving a packet including a destination address and first and second outputs. The cell includes a selection circuit for connecting the input with the first output or the second output depending on whether a specific bit occupying a predetermined position in the packet address is a logic "1" or a logic "0". Illustratively, the specific bit is the first bit after a start bit of the packer and each of the cells includes means for rotating the specific bit to the end of the address. This is especially useful for implementing a banyan network wherein the k.sup.th column of cells the routing decision is based on the k.sup.th most significant bit of the address, as the address bit rotation mechanism can be used to ensure that the first bit after the start bit of a packet is the k.sup.th most significant address bit. Preferably, each of the cells may be disabled in response to a disabling signal so that the input is connected to the first or second output independently of the logic value of the specific bit. This permits a packet switching network to be formed from interconnected horizontal and vertical stacks of chips wherein selected cells are disabled.